1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. More particularly, the present invention relates to a semiconductor device having a structure in which a semiconductor chip is mounted on a mounted body and a manufacturing method of the same.
2. Description of the Related Art
With improvement in integration, performance and function of LSIs, problems such as reduction in yield, increase in mounting area, and increase in cost become serious. In recent years, attention is paid to SiP (System in Package) in which both these problems and the LSI performance can be managed. The SiP can be classified into various structures such as a package lamination type, a chip stack type, and a chip-on-chip type, and particularly, the chip-on-chip type is advantageous in speedup and reduction in consumed electric power since chips can be multi-pin connected to each other with short wiring length.
The chip-on-chip type SiP is realized in such a way that for example, a memory chip and a logical circuit chip are connected to each other through micro bumps formed on the chip while the active surfaces of the chips are made to face each other face to face.
In general, in the chip-on-chip type SiP, a liquid resin called an underfill material is filled between the chips connected through the bumps in order to protect the bumps. The underfill material is filled between the chips by, for example, a method as shown in FIG. 19 (see, for example, JP-A-2005-276879 (patent document 1)). That is, a first semiconductor chip 1 and a second semiconductor chip 2 (including a not-shown diffusion layer, transistor, wiring layer, etc.) mounted thereon are connected to each other through bumps 3, and in this state, an underfill material 5 is supplied by using a needle 4. At this time, the underfill material 5 is dropped to the surface of the first semiconductor chip 1 in the vicinity of the second semiconductor chip 2. Then, the underfill material 5 wets and spreads on the surface of the first semiconductor chip 1, reaches the end of the second semiconductor chip 2, and penetrates a gap between the chips by a capillary phenomenon. Besides, as shown in FIGS. 20A and 20B, the underfill material 5 penetrated by the capillary phenomenon forms a fillet 6 with a wide bottom on the outer periphery of the second semiconductor chip 2. Thereafter, the underfill material 5 is hardened by heat treatment. By this, crack of the bumps 3 due to stress concentration is prevented, the influence of an external stress such as moisture absorption is reduced, and the connection reliability between the upper and lower chips is ensured.